Gridless Wire Routing using Cost Functions and Multiple Processors

The task of routing an electrical circuit can consume large amounts of time and memory. Attempts to speed this task have used fixed grids to limit the routing choices, global preprocessing to decompose the task into smaller subtasks, and multiple processors to do all of this in parallel. This paper describes a router that does not use a fixed grid, but instead allows the routes to run arbitrarily, limited only by blockages and design rules. Multiple parallel processors are used to speed up the routing of a single path as well as to find multiple routes at once. Finally, no global routing step is done because the parallel decomposer does much of this job when it assigns different routes to different processors. The router is implemented in the ElectricTM VLSI Design System [Rubin1983] and has demonstrated a speedup of over 4X on an 8-processor machine.